Dynamic and adaptive optimization of read compare levels based on memory cell threshold voltage distribution

ABSTRACT

A process is performed periodically or in response to an error in order to dynamically and adaptively optimize read compare levels based on memory cell threshold voltage distribution. One embodiment of the process includes determining threshold voltage distribution data for a population of non-volatile storage elements, smoothing the threshold voltage distribution data using a weighting function to create an interim set of data, determining a derivative of the interim set of data, and identifying and storing negative to positive zero crossings of the derivative as read compare points.

CLAIM OF PRIORITY

This application is a divisional application of U.S. patent applicationSer. No. 12/338,850, entitled “Dynamic And Adaptive Optimization Of ReadCompare Levels Based On Memory Cell Threshold Voltage Distribution”,filed Dec. 18, 2008, and claims the benefit of U.S. ProvisionalApplication No. 61/052,156 “Dynamic And Adaptive Optimization Of ReadCompare Levels Based On Memory Cell Threshold Voltage Distribution,” byNima Mokhlesi and Henry Chin, filed on May 9, 2008, incorporated hereinby reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to technology for non-volatile storage.

2. Description of the Related Art

Semiconductor memory has become more popular for use in variouselectronic devices. For example, non-volatile semiconductor memory isused in cellular telephones, digital cameras, personal digitalassistants, mobile computing devices, non-mobile computing devices andother devices. Electrical Erasable Programmable Read Only Memory(EEPROM) and flash memory are among the most popular non-volatilesemiconductor memories.

Both EEPROM and flash memory utilize a floating gate that is positionedabove and insulated from a channel region in a semiconductor substrate.The floating gate and channel regions are positioned between the sourceand drain regions. A control gate is provided over and insulated fromthe floating gate. The threshold voltage of the transistor is controlledby the amount of charge that is retained on the floating gate. That is,the minimum amount of voltage that must be applied to the control gatebefore the transistor is turned on to permit conduction between itssource and drain is controlled by the level of charge on the floatinggate.

When programming an EEPROM or flash memory device, such as a NAND flashmemory device, typically a program voltage is applied to the controlgate and the bit line is grounded. Electrons from the channel areinjected into the floating gate. When electrons accumulate in thefloating gate, the floating gate becomes negatively charged and thethreshold voltage of the memory cell is raised so that the memory cellis in a programmed state. More information about programming can befound in U.S. Pat. No. 6,859,397, titled “Source Side Self BoostingTechnique for Non-Volatile Memory;” U.S. Pat. No. 6,917,542, titled“Detecting Over Programmed Memory;” and U.S. Pat. No. 6,888,758, titled“Programming Non-Volatile Memory,” all three cited patents areincorporated herein by reference in their entirety.

In many cases, the program voltage is applied to the control gate as aseries of pulses (referred to as programming pulses), with the magnitudeof the pulses increasing at each pulse. Between programming pulses, aset of one or more verify operations are performed to determine whetherthe memory cell(s) being programmed have reached their target level. Ifa memory cell has reached its target level, programming stops for thatmemory cell. If a memory cell has not reached its target level,programming will continue for that memory cell.

Some EEPROM and flash memory devices have a floating gate that is usedto store two ranges of charges and, therefore, the memory cell can beprogrammed/erased between two states (an erased state and a programmedstate). Such a flash memory device is sometimes referred to as a binarymemory device.

A multi-state memory device stores multiple bits of data per memory cellby identifying multiple distinct valid threshold voltage distributions(or data states) separated by forbidden ranges. Each distinct thresholdvoltage distribution corresponds to a predetermined value for the set ofdata bits encoded in the memory device. For example, a memory cell thatstores two bits of data uses four valid threshold voltage distributions.A memory cell that stores three bits of data uses eight valid thresholdvoltage distributions.

Although non-volatile memory has proven to be very reliable, sometimeserrors can occur. Many memory systems uses Error Correction Codes (ECC)to correct errors found during a read process. Sometime, however, ECCcannot correct all errors.

SUMMARY OF THE INVENTION

A process is performed to dynamically and adaptively optimize the readcompare levels based on memory cell threshold voltage distribution. Theread compare levels are used to perform a read operation. By optimizingthe read compare levels, the accuracy of the read operation will beimproved.

One embodiment includes accessing threshold voltage distribution datafor a population of non-volatile storage elements, operating on thethreshold voltage distribution data to create transformed thresholdvoltage distribution data, and identifying read compare points based onthe transformed threshold voltage distribution data.

One embodiment includes accessing threshold voltage distribution datafor a population of non-volatile storage elements, smoothing thethreshold voltage distribution data, determining derivative informationfor the smoothed data, and identifying read compare points from thederivative information.

One embodiment includes determining threshold voltage distribution datafor a population of non-volatile storage elements, smoothing saidthreshold voltage distribution data using a weighted function to createan interim set of data, determining a derivative of the interim set ofdata, identifying new read compare values based on negative to positivezero crossings of the derivative, and performing one or more readoperations using the new read compare values.

One embodiment includes determining threshold voltage distribution datafor a population of flash memory devices, convolving said thresholdvoltage distribution data with a Gaussian function to create an interimset of data, determining a derivative of the interim set of data,identifying negative to positive zero crossings of the derivative,storing new read compare values based on the identified negative topositive zero crossings of the derivative, and performing one or moreread operations using the new read compare values.

One example implementation includes a two or three dimensional array ofnon-volatile storage elements and one or more managing circuits incommunication with the non-volatile storage elements. The one or moremanaging circuits perform any of the processes described herein,including accessing threshold voltage distribution data for a populationof non-volatile storage elements, smoothing the threshold voltagedistribution data, determining derivative information for the smootheddata, and identifying read compare points from the derivativeinformation.

One example implementation includes plurality of non-volatile storageelements, means for accessing threshold voltage distribution data forthe non-volatile storage elements, means for operating on the thresholdvoltage distribution data to create transformed threshold voltagedistribution data, and means for identifying read compare points basedon the transformed threshold voltage distribution.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a top view of a NAND string.

FIG. 2 is an equivalent circuit diagram of the NAND string.

FIG. 3 is a block diagram of a non-volatile memory system.

FIG. 4 is a block diagram depicting one embodiment of a memory array.

FIG. 5 is a block diagram depicting one embodiment of a sense block.

FIG. 6 depicts an example set of threshold voltage distributions.

FIG. 7 depicts an example set of threshold voltage distributions.

FIG. 8 depicts an example coding of data into a set of data statesassociated with threshold voltage distributions.

FIG. 9 depicts an example coding of data into a set of data statesassociated with threshold voltage distributions.

FIG. 10 is a flow chart describing one embodiment of operating anon-volatile memory system.

FIG. 11 is a flow chart describing one embodiment of programming anon-volatile memory system.

FIG. 12 is a signal diagram depicting a read operation.

FIG. 13 depicts an example set of threshold voltage distributions.

FIG. 14 is a flow chart describing one embodiment of read data in anon-volatile memory system.

FIG. 15 is a flow chart describing one embodiment of a process performedfor updating a non-volatile memory system during idle time.

FIG. 16 is a flow chart describing one embodiment of a process forupdating read compare levels.

FIG. 17 is a flow chart describing one embodiment of a process fordetermining threshold voltage distribution data.

FIG. 18 is a graph of threshold voltage distribution data.

FIG. 19 is a graph showing the result of a derivative calculation

FIG. 20 20A is a flow chart describing one embodiment of a process forupdating read compare levels.

FIG. 20A 20B depicts a truncated Gaussian curve.

FIG. 21 21A is a flow chart describing one embodiment of a process forupdating read compare levels.

FIG. 21A 21B depicts an asymmetrical threshold voltage distribution.

FIG. 22 is a flow chart describing one embodiment of a process forupdating read compare levels.

FIG. 23 is a flow chart describing one embodiment of a process forupdating read compare levels.

FIG. 24 is a flow chart describing one embodiment of a process forupdating read compare levels.

FIG. 25 is a flow chart describing one embodiment of a process forupdating read compare levels.

DETAILED DESCRIPTION

One example of a flash memory system uses the NAND structure, whichincludes arranging multiple transistors in series, sandwiched betweentwo select gates. The transistors in series and the select gates arereferred to as a NAND string. FIG. 1 is a top view showing one NANDstring. FIG. 2 is an equivalent circuit thereof. The NAND stringdepicted in FIGS. 1 and 2 includes four transistors 100, 102, 104 and106 in series and sandwiched between a first (or drain side) select gate120 and a second (or source side) select gate 122. Select gate 120connects the NAND string to a bit line via bit line contact 126. Selectgate 122 connects the NAND string to source line 128. Select gate 120 iscontrolled by applying the appropriate voltages to select line SGD.Select gate 122 is controlled by applying the appropriate voltages toselect line SGS. Each of the transistors 100, 102, 104 and 106 has acontrol gate and a floating gate. For example, transistor 100 hascontrol gate 100CG and floating gate 100FG. Transistor 102 includescontrol gate 102CG and a floating gate 102FG. Transistor 104 includescontrol gate 104CG and floating gate 104FG. Transistor 106 includes acontrol gate 106CG and a floating gate 106FG. Control gate 100CG isconnected to word line WL3, control gate 102CG is connected to word lineWL2, control gate 104CG is connected to word line WL1, and control gate106CG is connected to word line WL0.

Note that although FIGS. 1 and 2 show four memory cells in the NANDstring, the use of four transistors is only provided as an example. ANAND string can have fewer than four memory cells or more than fourmemory cells. For example, some NAND strings will include eight memorycells, 16 memory cells, 32 memory cells, 64 memory cells, 128 memorycells, etc. The discussion herein is not limited to any particularnumber of memory cells in a NAND string.

A typical architecture for a flash memory system using a NAND structurewill include several NAND strings. Each NAND string is connected to thesource line by its source select gate controlled by select line SGS andconnected to its associated bit line by its drain select gate controlledby select line SGD. Each bit line and the respective NAND string(s) thatare connected to that bit line via a bit line contact comprise thecolumns of the array of memory cells. Bit lines are shared with multipleNAND strings. Typically, the bit line runs on top of the NAND strings ina direction perpendicular to the word lines and is connected to one ormore sense amplifiers.

Each memory cell can store data (analog or digital). When storing onebit of digital data, the range of possible threshold voltages of thememory cell is divided into two ranges which are assigned logical data“1” and “0.” In one example of a NAND type flash memory, the thresholdvoltage is negative after the memory cell is erased, and defined aslogic “1.” The threshold voltage after programming is positive anddefined as logic “0.” When the threshold voltage is negative and a readis attempted by applying 0 volts to the control gate, the memory cellwill turn on to indicate logic one is being stored. When the thresholdvoltage is positive and a read operation is attempted by applying 0volts to the control gate, the memory cell will not turn on, whichindicates that logic zero is stored.

In the case of storing multiple levels of data, the range of possiblethreshold voltages is divided into the number of levels of data. Forexample, if four levels of information is stored (two bits of data),there will be four threshold voltage ranges assigned to the data values“11”, “10”, “01”, and “00.” In one example of a NAND type memory, thethreshold voltage after an erase operation is negative and defined as“11”. Positive threshold voltages are used for the data states of “10”,“01”, and “00.” If eight levels of information (or states) are stored(e.g. for three bits of data), there will be eight threshold voltageranges assigned to the data values “000”, “001”, “010”, “011” “100”,“101”, “110” and “111.”

The specific relationship between the data programmed into the memorycell and the threshold voltage levels of the cell depends upon the dataencoding scheme adopted for the cells. For example, U.S. Pat. No.6,222,762 and U.S. Patent Application Publication No. 2004/0255090, bothof which are incorporated herein by reference in their entirety,describe various data encoding schemes for multi-state flash memorycells. In one embodiment, data values are assigned to the thresholdvoltage ranges using a Gray code assignment so that if the thresholdvoltage of a floating gate erroneously shifts to its neighboringphysical state, only one bit will be affected. In some embodiments, thedata encoding scheme can be changed for different word lines, the dataencoding scheme can be changed over time, or the data bits for randomword lines may be inverted or otherwise randomized to reduce datapattern sensitivity and even wear on the memory cells.

Relevant examples of NAND type flash memories and their operation areprovided in the following U.S. patents/patent applications, all of whichare incorporated herein by reference: U.S. Pat. No. 5,570,315; U.S. Pat.No. 5,774,397; U.S. Pat. No. 6,046,935; U.S. Pat. No. 6,456,528; andU.S. Pat. Publication No. US2003/0002348. The discussion herein can alsoapply to other types of flash memory in addition to NAND as well asother types of non-volatile memory.

Other types of non-volatile storage devices, in addition to NAND flashmemory, can also be used. For example, a so called TANOS structure(consisting of a stacked layer of TaN—Al2O3-SiN—SiO2 on a siliconsubstrate), which is basically a memory cell using trapping of charge ina nitride layer (instead of a floating gate), can also be used with thepresent invention. Another type of memory cell useful in flash EEPROMsystems utilizes a non-conductive dielectric material in place of aconductive floating gate to store charge in a non-volatile manner. Sucha cell is described in an article by Chan et al., “A TrueSingle-Transistor Oxide-Nitride-Oxide EEPROM Device,” IEEE ElectronDevice Letters, Vol. EDL-8, No. 3, March 1987, pp. 93-95. A triple layerdielectric formed of silicon oxide, silicon nitride and silicon oxide(“ONO”) is sandwiched between a conductive control gate and a surface ofa semi-conductive substrate above the memory cell channel. The cell isprogrammed by injecting electrons from the cell channel into thenitride, where they are trapped and stored in a limited region. Thisstored charge then changes the threshold voltage of a portion of thechannel of the cell in a manner that is detectable. The memory cell iserased by injecting hot holes into the nitride. See also Nozaki et al.,“A 1-Mb EEPROM with MONOS Memory Cell for Semiconductor DiskApplication,” IEEE Journal of Solid-State Circuits, Vol. 26, No. 4,April 1991, pp. 497-501, which describes a similar memory cell in asplit-gate configuration where a doped polysilicon gate extends over aportion of the memory cell channel to form a separate select transistor.The foregoing two articles are incorporated herein by reference in theirentirety. The programming techniques mentioned in section 1.2 of“Nonvolatile Semiconductor Memory Technology,” edited by William D.Brown and Joe E. Brewer, IEEE Press, 1998, incorporated herein byreference, are also described in that section to be applicable todielectric charge-trapping devices. Other types of memory devices(utilizing floating gates or not utilizing floating gates) can also beused.

FIG. 3 illustrates a non-volatile storage device 210 that may includeone or more memory die or chips 212. Memory die 212 includes an array(two-dimensional or three dimensional) of memory cells 200, controlcircuitry 220, and read/write circuits 230A and 230B. In one embodiment,access to the memory array 200 by the various peripheral circuits isimplemented in a symmetric fashion, on opposite sides of the array, sothat the densities of access lines and circuitry on each side arereduced by half The read/write circuits 230A and 230B include multiplesense blocks 300 which allow a page of memory cells to be read orprogrammed in parallel. The memory array 100 is addressable by wordlines via row decoders 240A and 240B and by bit lines via columndecoders 242A and 242B. In a typical embodiment, a controller 244 isincluded in the same memory device 210 (e.g., a removable storage cardor package) as the one or more memory die 212. Commands and data aretransferred between the host and controller 244 via lines 232 andbetween the controller and the one or more memory die 212 via lines 234.One implementation can include multiple chips 212.

Control circuitry 220 cooperates with the read/write circuits 230A and230B to perform memory operations on the memory array 200. The controlcircuitry 220 includes a state machine 222, an on-chip address decoder224 and a power control module 226. The state machine 222 provideschip-level control of memory operations. The on-chip address decoder 224provides an address interface between that used by the host or a memorycontroller to the hardware address used by the decoders 240A, 240B,242A, and 242B. The power control module 226 controls the power andvoltages supplied to the word lines and bit lines during memoryoperations. In one embodiment, power control module 226 includes one ormore charge pumps that can create voltages larger than the supplyvoltage.

In one embodiment, one or any combination of control circuitry 220,power control circuit 226, decoder circuit 224, state machine circuit222, decoder circuit 242A, decoder circuit 242B, decoder circuit 240A,decoder circuit 240B, read/write circuits 230A, read/write circuits230B, and/or controller 244 can be referred to as one or more managingcircuits.

FIG. 4 depicts an exemplary structure of memory cell array 200. In oneembodiment, the array of memory cells is divided into M blocks of memorycells. As is common for flash EEPROM systems, the block is the unit oferase. That is, each block contains the minimum number of memory cellsthat are erased together. Each block is typically divided into a numberof pages. A page is a unit of programming. One or more pages of data aretypically stored in one row of memory cells. A page can store one ormore sectors. A sector includes user data and overhead data. Overheaddata typically includes an Error Correction Code (ECC) that has beencalculated from the user data of the sector. A portion of the controller(described below) calculates the ECC when data is being programmed intothe array, and also checks it when data is being read from the array.Alternatively, the ECCs and/or other overhead data are stored indifferent pages, or even different blocks, than the user data to whichthey pertain. A sector of user data is typically 512 bytes,corresponding to the size of a sector in magnetic disk drives. A largenumber of pages form a block, anywhere from 8 pages, for example, up to32, 64, 128 or more pages. Different sized blocks and arrangements canalso be used.

In another embodiment, the bit lines are divided into odd bit lines andeven bit lines. In an odd/even bit line architecture, memory cells alonga common word line and connected to the odd bit lines are programmed atone time, while memory cells along a common word line and connected toeven bit lines are programmed at another time.

FIG. 4 shows more details of block i of memory array 200. Block iincludes X+1 bit lines and X+1 NAND strings. Block i also includes 64data word lines (WL0-WL63), 2 dummy word lines (WL_d0 and WL_d1), adrain side select line (SGD) and a source side select line (SGS). Oneterminal of each NAND string is connected to a corresponding bit linevia a drain select gate (connected to select line SGD), and anotherterminal is connected to the source line via a source select gate(connected to select line SGS). Because there are sixty four data wordlines and two dummy word lines, each NAND string includes sixty fourdata memory cells and two dummy memory cells. In other embodiments, theNAND strings can have more or less than 64 data memory cells and twodummy memory cells. Data memory cells can store user or system data.Dummy memory cells are typically not used to store user or system data.Some embodiments do not include dummy memory cells.

FIG. 5 is a block diagram of an individual sense block 300 partitionedinto a core portion, referred to as a sense module 480, and a commonportion 490. In one embodiment, there will be a separate sense module480 for each bit line and one common portion 490 for a set of multiplesense modules 480. In one example, a sense block will include one commonportion 490 and eight sense modules 480. Each of the sense modules in agroup will communicate with the associated common portion via a data bus472. For further details, refer to U.S. Patent Application Publication2006/0140007, which is incorporated herein by reference in its entirety.

Sense module 480 comprises sense circuitry 470 that determines whether aconduction current in a connected bit line is above or below apredetermined threshold level. In some embodiments, sense module 480includes a circuit commonly referred to as a sense amplifier. Sensemodule 480 also includes a bit line latch 482 that is used to set avoltage condition on the connected bit line. For example, apredetermined state latched in bit line latch 482 will result in theconnected bit line being pulled to a state designating program inhibit(e.g., Vdd).

Common portion 490 comprises a processor 492, a set of data latches 494and an I/O Interface 496 coupled between the set of data latches 494 anddata bus 420. Processor 492 performs computations. For example, one ofits functions is to determine the data stored in the sensed memory celland store the determined data in the set of data latches. The set ofdata latches 494 is used to store data bits determined by processor 492during a read operation. It is also used to store data bits importedfrom the data bus 420 during a program operation. The imported data bitsrepresent write data meant to be programmed into the memory. I/Ointerface 496 provides an interface between data latches 494 and thedata bus 420.

During read or sensing, the operation of the system is under the controlof state machine 222 that controls the supply of different control gatevoltages to the addressed cell. As it steps through the variouspredefined control gate voltages corresponding to the various memorystates supported by the memory, the sense module 480 may trip at one ofthese voltages and an output will be provided from sense module 480 toprocessor 492 via bus 472. At that point, processor 492 determines theresultant memory state by consideration of the tripping event(s) of thesense module and the information about the applied control gate voltagefrom the state machine via input lines 493. It then computes a binaryencoding for the memory state and stores the resultant data bits intodata latches 494. In another embodiment of the core portion, bit linelatch 482 serves double duty, both as a latch for latching the output ofthe sense module 480 and also as a bit line latch as described above.

It is anticipated that some implementations will include multipleprocessors 492. In one embodiment, each processor 492 will include anoutput line (not depicted in FIG. 5) such that each of the output linesis wired-OR'd together. In some embodiments, the output lines areinverted prior to being connected to the wired-OR line. Thisconfiguration enables a quick determination during the programverification process of when the programming process has completedbecause the state machine receiving the wired-OR line can determine whenall bits being programmed have reached the desired level. For example,when each bit has reached its desired level, a logic zero for that bitwill be sent to the wired-OR line (or a data one is inverted). When allbits output a data 0 (or a data one inverted), then the state machineknows to terminate the programming process. In embodiments where eachprocessor communicates with eight sense modules, the state machine may(in some embodiments) need to read the wired-OR line eight times, orlogic is added to processor 492 to accumulate the results of theassociated bit lines such that the state machine need only read thewired-OR line one time.

During program or verify, the data to be programmed is stored in the setof data latches 494 from the data bus 420. The program operation, underthe control of the state machine, comprises a series of programmingvoltage pulses (with increasing magnitudes) applied to the control gatesof the addressed memory cells. Each programming pulse is followed by averify process to determine if the memory cell has been programmed tothe desired state. Processor 492 monitors the verified memory staterelative to the desired memory state. When the two are in agreement,processor 492 sets the bit line latch 482 so as to cause the bit line tobe pulled to a state designating program inhibit. This inhibits the cellcoupled to the bit line from further programming even if it is subjectedto programming pulses on its control gate. In other embodiments theprocessor initially loads the bit line latch 482 and the sense circuitrysets it to an inhibit value during the verify process.

Data latch stack 494 contains a stack of data latches corresponding tothe sense module. In one embodiment, there are 3-5 (or another number)data latches per sense module 480. In one embodiment, the latches areeach one bit. In some implementations (but not required), the datalatches are implemented as a shift register so that the parallel datastored therein is converted to serial data for data bus 420, and viceversa. In one preferred embodiment, all the data latches correspondingto the read/write block of m memory cells can be linked together to forma block shift register so that a block of data can be input or output byserial transfer. In particular, the bank of read/write modules isadapted so that each of its set of data latches will shift data in to orout of the data bus in sequence as if they are part of a shift registerfor the entire read/write block.

Additional information about the read operations and sense amplifierscan be found in (1) United States Patent Application Pub. No.2004/0057287, “Non-Volatile Memory And Method With Reduced Source LineBias Errors,” published on Mar. 25, 2004; (2) United States PatentApplication Pub No. 2004/0109357, “Non-Volatile Memory And Method withImproved Sensing,” published on Jun. 10, 2004; (3) U.S. PatentApplication Pub. No. 20050169082; (4) U.S. Patent Publication2006/0221692, titled “Compensating for Coupling During Read Operationsof Non-Volatile Memory,” Inventor Jian Chen, filed on Apr. 5, 2005; and(5) U.S. patent application Ser. No. 11/321,953, titled “Reference SenseAmplifier For Non-Volatile Memory, Inventors Siu Lung Chan andRaul-Adrian Cernea, filed on Dec. 28, 2005. All five of the immediatelyabove-listed patent documents are incorporated herein by reference intheir entirety.

At the end of a successful programming process (with verification), thethreshold voltages of the memory cells should be within one or moredistributions of threshold voltages for programmed memory cells orwithin a distribution of threshold voltages for erased memory cells, asappropriate. FIG. 6 illustrates example threshold voltage distributionscorresponding to data states for the memory cell array when each memorycell stores four bits of data. Other embodiment, however, may use moreor less than four bits of data per memory cell. FIG. 6 shows sixteenthreshold voltage distributions corresponding to data states 0-15. Inone embodiment, the threshold voltages in state 0 are negative and thethreshold voltages in the states 1-15 are positive. The division of datastates being positive or negative is not limited by the technologydescribed herein.

In one embodiment five states are in negative voltages and eleven statesare in positive voltages. To sense data for the negative voltages, thep-well and source lines can be driven (e.g. 1.6 volts) to allow fornegative sensing.

Between each pair of adjacent states in the data states 0-15 is a readreference voltage used for reading data from memory cells. For example,FIG. 6 shows read reference voltage Vra between data states 0 and 1, andVrb between data states 1 and 2. By testing whether the thresholdvoltage of a given memory cell is above or below the respective readreference voltages, the system can determine what state the memory cellis in.

At or near the lower edge of each data state 0-15 is a verify referencevoltage. For example, FIG. 6 shows Vv1 for state 1 and Vv2 for state 2.When programming memory cells to a given state, the system will testwhether those memory cells have a threshold voltage greater than orequal to the verify reference voltage.

FIG. 7 illustrates that another embodiment of threshold voltagedistributions corresponding to data states 0-15 that can partiallyoverlap since the ECC can handle a certain percentage of cells that arein error.

Also note that the Vt axis may be offset from actual voltages applied tothe control gates as body effect through source and p-well or bodybiasing is used to shift negative threshold voltage into the measurablepositive range. Another point to note is that contrary to the equalspacing/width of the depicted sixteen states, various states may havedifferent widths/spacings in order to accommodate varying amounts ofsusceptibility to retention loss. In some embodiments, states 0 and/or15 are wider than the other states. In other embodiment, states near thecenter of the Vt window will be more closely spaced than states near thetwo edges of the window, creating a more gradual change in state widths.

Each data state of FIG. 6 or FIG. 7 corresponds to predetermined valuesfor the data bits stored in the memory cells programmed to therespective states.

FIG. 8 is a table providing an example of the data values assigned toeach data state 0-15. In one embodiment, a memory cell stores data infour different pages. The four pages are referred to as the 1^(st) lowerpage, 2^(nd) upper page, 3^(rd) higher page and 4^(th) top page. FIG. 8depicts the data in each page for each data state 0-15. In oneembodiment, each page is programmed separately. In another embodiment,all four data bits for a memory cell are programmed at the same time.

FIG. 9 is a table providing another example of the data values assignedto each data state 0-15. The data values of FIG. 9 utilize a Gray codeassignment so that only one bit changes between neighboring data states.This arrangement reduces the number of error bits if the thresholdvoltage of a memory cells is too low or too high.

FIG. 10 is a flow chart describing a process for operating memory cellsconnected to a selected word line. In one embodiment, the process ofFIG. 10 is used to program a block of memory cells. In oneimplementation of the process of FIG. 10, memory cells arepre-programmed in order to maintain even wear on the memory cells (step550). In one embodiment, the memory cells are preprogrammed to state 15,a random pattern, or any other pattern. In some implementations,pre-programming need not be performed.

In step 552, memory cells are erased (in blocks or other units) prior toprogramming. Memory cells are erased in one embodiment by raising thep-well to an erase voltage (e.g., 20 volts) for a sufficient period oftime and grounding the word lines of a selected block while the sourceand bit lines are floating. In blocks that are not selected to beerased, word lines are floated. Due to capacitive coupling, theunselected word lines, bit lines, select lines, and the common sourceline are also raised to a significant fraction of the erase voltagethereby impeding erase on blocks that are not selected to be erased. Inblocks that a selected to be erased, a strong electric field is appliedto the tunnel oxide layers of selected memory cells and the selectedmemory cells are erased as electrons of the floating gates are emittedto the substrate side, typically by Fowler-Nordheim tunneling mechanism.As electrons are transferred from the floating gate to the p-wellregion, the threshold voltage of a selected cell is lowered. Erasing canbe performed on the entire memory array, on individual blocks, oranother unit of cells. In one embodiment, after erasing the memorycells, all of the erased memory cells will be in state 0 (see FIGS. 6 &7). One implementation of an erase process includes applying severalerase pulses to the p-well and verifying between erase pulses whetherthe NAND strings are properly erased.

At step 554, soft programming is performed to narrow the distribution oferased threshold voltages for the erased memory cells. Some memory cellsmay be in a deeper erased state than necessary as a result of the eraseprocess. Soft programming can apply programming pulses to move thethreshold voltage of the deeper erased memory cells closer to the eraseverify level. In step 556, the memory cells of the block are programmed.The process of FIG. 10 can be performed at the direction of the statemachine using the various circuits described above. In otherembodiments, the process of FIG. 10 can be performed at the direction ofthe controller using the various circuits described above. Afterperforming the process of FIG. 10, the memory cells of the block can beread (step 558). FIG. 10 shows that the erase-program cycle can happenmany times without or independent of reading, the read process can occurmany times without or independent of programming, and the read processcan happen any time after programming.

FIG. 11 is a flow chart describing one embodiment of a process forperforming programming on memory cells connected to a common word line.The process of FIG. 10 can be performed one or multiple times duringstep 556 of FIG. 10. The process of FIG. 11 can be used to programmemory cells from state 0 directly to any of states 1-15. Alternatively,the process of FIG. 15 can be used as part of another programmingprocess, such as those disclosed in U.S. Pat. No. 7,196,928. Manydifferent programming processes are known in the art. The technologydescribed herein is not limited to any particular process forprogramming. Many different programming processes will work with thetechnology described herein.

Typically, the program voltage applied to the control gate during aprogram operation is applied as a series of program pulses. In betweenprogramming pulses are a set of verify pulses to enable verification. Inmany implementations, the magnitude of the program pulses is increasedwith each successive pulse by a predetermined step size. In step 608 ofFIG. 11, the programming voltage (Vpgm) is initialized to the startingmagnitude (e.g., ˜12-16V or another suitable level) and a programcounter PC maintained by state machine 222 is initialized at 1. In step610, a program pulse of the program signal Vpgm is applied to theselected word line (the word line selected for programming). Theunselected word lines receive one or more boosting voltages (e.g., ˜9volts) to perform boosting schemes known in the art. If a memory cellshould be programmed, then the corresponding bit line is grounded. Onthe other hand, if the memory cell should remain at its currentthreshold voltage, then the corresponding bit line is connected toV_(DD) to inhibit programming. More information about boosting schemescan be found in U.S. Pat. No. 6,859,397 and U.S. patent application Ser.No. 11/555,850, both of which are incorporated herein by reference.

In step 610, the program pulse is concurrently applied to all memorycells connected to the selected word line so that all of the memorycells connected to the selected word line are programmed together. Thatis, they are programmed at the same time (or during overlapping times).In this manner all of the memory cells connected to the selected wordline will concurrently have their threshold voltage change, unless theyhave been locked out from programming.

In step 612, the states of the selected memory cells are verified usingthe appropriate set of target levels. Step 612 of FIG. 10 includesperforming one or more verify operations. If it is detected that thethreshold voltage of a selected memory cell has reached the appropriatetarget level, then the memory cell is locked out of further programmingby, for example, raising its bit line voltage to Vdd during subsequentprogramming pulses. In step 614 it is checked whether all of memorycells have reached their target threshold voltages. If so, theprogramming process is complete and successful because all selectedmemory cells were programmed and verified to their target states. Astatus of “PASS” is reported in step 616. Note that in someimplementations, in step 614 it is checked whether at least apredetermined number of memory cells have been properly programmed. Thispredetermined number can be less than the number of all memory cells,thereby allowing the programming process to stop before all memory cellshave reached their appropriate verify levels. The memory cells that arenot successfully programmed can be corrected using error correctionduring the read process.

If, in step 614, it is determined that not all of the memory cells havereached their target threshold voltages, then the programming processcontinues. In step 618, the program counter PC is checked against theprogram limit value (PL). One example of a program limit value is 20;however, other values can be used. If the program counter PC is not lessthan the program limit value, then it is determined in step 630 whetherthe number of memory cells that have not been successfully programmed isequal to or less than a predetermined number. If the number ofunsuccessfully programmed memory cells is equal to or less than thepredetermined number, then the programming process is flagged as passedand a status of PASS is reported in step 632. In many cases, the memorycells that are not successfully programmed can be corrected using errorcorrection during the read process. If however, the number ofunsuccessfully programmed memory cells is greater than the predeterminednumber, the program process is flagged as failed and a status of FAIL isreported in step 634.

If, in step 618, it is determined that the Program Counter PC is lessthan the Program Limit value PL, then the process continues at step 620during which time the Program Counter PC is incremented by 1 and theprogram voltage Vpgm is stepped up to the next magnitude. For example,the next pulse will have a magnitude greater than the previous pulse bya step size (e.g., a step size of 0.1-0.4 volts). After step 620, theprocess loops back to step 610 and another program pulse is applied tothe selected word line.

FIG. 12 is a timing diagram depicting the behavior of various signalsduring one iteration of a read or verify process. For example, if thememory cells are binary memory cells, the process of FIG. 12 may beperformed once for each memory cell during an iteration of step 612 orduring a read process. If the memory cells are multi-state memory cellswith sixteen states (e.g., states 0-15), the process of FIG. 12 may beperformed fifteen times for each memory cell during an iteration of step612 or during an attempt to read the data from the memory cell. Forexample, between each data state is a read compare point, such as Vrabetween state 0 and state 1 of FIG. 6 and Vrb between state 1 and state2 of FIG. 6. There would be additional read compare points between theother sets of neighboring states. A read process would test whether thethreshold voltage of a memory cell was below each of the fifteen readcompare points. Based on the results of the fifteen tests, it can bedetermined which state the memory cell is in. For example, if the memorycell has a threshold voltage lower than Vrb but not lower then Vra, thenthe memory cell is in state 2. The verify process works in a similarmanner, except the verify compare points Vva, Vvb, . . . are usuallylocated at or near the lower edge of the state.

In general, during the read and verify operations, the selected wordline is connected to a voltage, a level of which is specified for eachread and verify operation in order to determine whether a thresholdvoltage of the concerned memory cell has reached such level. Afterapplying the word line voltage, the conduction current of the memorycell is measured to determine whether the memory cell turned on inresponse to the voltage applied to the word line. If the conductioncurrent is measured to be greater than a certain value, then it isassumed that the memory cell turned on and the voltage applied to theword line is greater than the threshold voltage of the memory cell. Ifthe conduction current is not measured to be greater than the certainvalue, then it is assumed that the memory cell did not turn on and thevoltage applied to the word line is not greater than the thresholdvoltage of the memory cell.

There are many ways to measure the conduction current of a memory cellduring a read or verify operation. In one example, the conductioncurrent of a memory cell is measured by the rate it discharges orcharges a dedicated capacitor in the sense amplifier. In anotherexample, the conduction current of the selected memory cell allows (orfails to allow) the NAND string that included the memory cell todischarge a voltage on the bit line. The charge on the bit line ismeasured after a period of time to see whether it has been discharged ornot. FIG. 12 explains both examples.

FIG. 12 shows signals SGD, WL_unsel., WLn, SGS, Selected BL, and Sourcestarting at Vss (approximately 0 volts). SGD represents the gate of thedrain side select gate. SGS is the gate of the source side select gate.WLn is the word line selected for reading/verification. WL_unselrepresents the unselected word lines. Selected BL is the voltage of thebit line selected for reading/verification. Source is the source linefor the memory cells (see FIG. 4). Note that there are two versions ofSGS and Selected BL. One set of these signals SGS (B) and Selected BL(B) depict a read/verify operation for an array of memory cells thatmeasure the conduction current of a memory cell by determining whetherthe bit line has discharged. Another set of these signals SGS (C) andSelected BL (C) depict a read/verify operation for an array of memorycells that measure the conduction current of a memory cell by the rateit discharges a dedicated capacitor in the sense amplifier.

First, the behavior of the sensing circuits and the array of memorycells that are involved in measuring the conduction current of a memorycell by determining whether the bit line has discharged will bediscussed with respect to SGS (B) and Selected BL (B). At time t1 ofFIG. 12, SGD is raised to Vdd (e.g., approximately 3.5 volts), theunselected word lines (WL_unsel) are raised to Vread (e.g.,approximately 5.5 volts), the selected word line WLn is raised t0 theread compare voltage Vcgr (e.g., Vra, Vrb, . . . ) for a read operationor a verify compare level (e.g., Vva, Vvb, . . . ) for a verifyoperation. The voltage Vread act as an overdrive or pass voltage becauseit causes the unselected memory cells to turn on and act as pass gates.At time t2, the source side select gate is turned on by raising SGS (B)to Vdd. This provides a path to dissipate the charge on the bit line. Ifthe threshold voltage of the memory cell selected for reading is greaterthan Vcgr or the verify compare level applied to the selected word lineWLn, then the selected memory cell will not turn on and the bit linewill not discharge, as depicted by signal line 450. If the thresholdvoltage in the memory cell selected for reading is below Vcgr or belowthe verify compare level applied to the selected word line WLn, then thememory cell selected for reading will turn on (conduct) and the bit linevoltage will dissipate, as depicted by curve 452. At some point aftertime t2 and prior to time t3 (as determined by the particularimplementation), the sense amplifier will determine whether the bit linehas dissipated a sufficient amount. At time t3, the depicted signalswill be lowered to Vss (or another value for standby or recovery). Notethat in other embodiments, the timing of some of the signals can bechanged (e.g. shift the signal applied to the neighbor).

Next, the behavior of the sensing circuits and the array of memory cellsthat measure the conduction current of a memory cell by the rate itdischarges a dedicated capacitor in the sense amplifier will bediscussed with respect to SGS (C) and Selected BL (C). At time t1 ofFIG. 12, SGD is raised to Vdd (e.g., approximately 3.5 volts), theunselected word lines (WL_unsel) are raised to Vread (e.g.,approximately 5.5 volts), the selected word line WLn is raised to readcompare level Vcgr for a read operation or a verify compare level for averify operation. In this case, the sense amplifier holds the bit linevoltage constant regardless of what the NAND sting is doing, so thesense amplifier measures the current flowing with the bit line “clamped”to that voltage. At some point after time t1 and prior to time t3 (asdetermined by the particular implementation), the sense amplifier willdetermine whether the capacitor in the sense amplifier has dissipated asufficient amount. At time t3, the depicted signals will be lowered toVss (or another value for standby or recovery). Note that in otherembodiments, the timing of some of the signals can be changed.

Looking back at FIG. 6, the read compare points Vra and Vrb are between,but not within, any of the data states (threshold voltagedistributions). In FIG. 7, however, the sixteen data states (thresholdvoltage distributions) are overlapping. Therefore, the read comparepoints will likely be (but are not required to be) within one or two ofthe data states (threshold voltage distributions). For example, FIG. 7shows fifteen read compare points (or voltage levels) Vr1, Vr2, Vr3,Br4, Vr5, Vr6, Vr7, Vr8, Vr9, Vr10, Vr11, Vr12, Vr13, Vr14 and Vr15. Vr1is depicted to be within the intersection of state 0 and state 1. Vr2 isdepicted to be within the intersection of state 1 and state 2. Vr3 isdepicted to be within the intersection of state 2 and state 3. Vr4 isdepicted to be within the intersection of state 3 and state 4. Vr5 isdepicted to be within the intersection of state 4 and state 5. Vr6 isdepicted to be within the intersection of state 5 and state 6. Vr7 isdepicted to be within the intersection of state 6 and state 7. Vr8 isdepicted to be within the intersection of state 7 and state 8. Vr9 isdepicted to be within the intersection of state 8 and state 9. Vr10 isdepicted to be within the intersection of state 9 and state 10. Vr11 isdepicted to be within state the intersection of 10 and state 11. Vr12 isdepicted to be within state the intersection of 1 and state 12. Vr13 isdepicted to be within the intersection of state 12 and state 13. Vr14 isdepicted to be within the intersection of state 13 and state 14. Vr15 isdepicted to be within the intersection of state 14 and state 15.

By determining whether a memory cell conducts current in response to thefifteen read compare points, it is possible to determine which state thememory cell is in. For example, if the memory cell conducts in responseto Vr1, the memory cell is in state 0. If the memory cell only conductsin response to Vr15, the memory cell is in state 14. If the memory celldoes not conduct in response to any of the read compare points, then thememory cell is in state 15. If the memory cell does not conduct inresponse to Vr1, Vr2 and Vr3, but does conduct in response to Vr4, thenthe memory cell is in state 3. And so on.

As depicted, the data states (threshold voltage distributions) of FIG. 7are overlapping. Thus, some memory cells in state 4 may have a thresholdvoltage that is in the intersection of states 3 and 4, and may be belowVr4. It is anticipated, that if the read compare points are setproperly, then any potential errors due to the memory cells being in theintersection of below/above read compare point will be taken care of byECC. However, if the read compare points are not accurate, then therecould be an error when reading the data.

For various reasons, a population of non-volatile memory cells couldhave their threshold voltages drift over time. Data retention issuescausing charge loss/gain, program disturb, temperature differencebetween the time the cells were programmed and the time that they areread, read disturb, back pattern effect, and capacitive coupling betweenadjacent floating gates are all phenomena known in the art for causingchanges to threshold voltages (or apparent threshold voltages) ofnon-volatile memory cells. A shifting of threshold voltages for apopulation of memory cells can cause the read compare points to beinaccurate. For example, FIG. 13 shows the data states (thresholdvoltage distributions) of FIG. 7 after a shift of the threshold voltagesof the entire population of memory cells. As can be seen, the readcompare points Vr1, Vr2, . . . , Vr15 are no longer lined up properly.This can cause an error when reading data. Therefore, the technologydescribed herein seeks to dynamically and adaptively update the readcompare points (voltage levels) based on memory cell threshold voltagedistribution. One embodiment updates the read compare points when anerror occurs. Another embodiment updates the read compare pointsperiodically when the memory system has idle time or can otherwiseperform the operation without materially effecting user perceivedperformance.

FIG. 14 is a flow chart describing a process for reading data thatupdates the read compare points when an error occurs. FIG. 15 is a flowchart describing a process for reading data that updates the readcompare points periodically when the memory system has idle time or canotherwise perform the operation without materially effecting userperceived performance. It is possible for a memory system to implementthe processes of both FIG. 14 and FIG. 15.

FIG. 14 provides the read process at the system level. In step 700, arequest to read data is received. In step 702, a read operation isperformed for a particular page in response to the request to read data.In one embodiment, when data for a page is programmed, the system willalso create extra bits used for Error Correction Codes (ECCs) and writethose ECC bits along with the page of data. ECC technologies are wellknown in the art. The ECC process used can include any suitable ECCprocess known in the art. When reading data from a page, the ECC bitswill be used to determine whether there are any errors in the data (step704). The ECC process can be performed by the controller, the statemachine or elsewhere in the system. If there are no errors in the data,the data is reported at step 706. For example, data will be communicatedto a controller or host. If an error is found at step 704, it isdetermined whether the error is correctable (step 708). Various ECCmethods have the ability to correct a predetermined number of errors ina set of data. If the ECC process can correct the data, then the ECCprocess is used to correct and recover that data in step 710 and thedata, as corrected, is reported to the host or controller in step 712.

If the data is not correctable by the ECC process, a data recoveryprocess is performed. In a certain class of ECC schemes, namely StrongECC (or SECC), when the ECC engine is presented with an overwhelmingnumber of bad bits on a page, the SECC engine will continue itsiterative process and will never converge to the correct answer.Therefore, if the SECC engine takes too long to correct the data, theiterative convergence process can be stopped, and a data recoveryprocess can be performed. In step 714, the read compare levels for thedata attempted to be read will be updated. In step 716, a read processwill be performed using the new read compare levels in order todetermine the data stored in the memory cells. In step 718, the datawill be reported to the host or controller. The read process of steps702 and 716 include performing the operation of FIG. 12 for each readcompare point and then determining the appropriate data state for eachmemory cell.

FIG. 15 is a flow chart describing a process for reading data thatupdates the read compare points periodically when the memory system hasidle time or can otherwise perform the operation without materiallyeffecting user perceived performance. The process of FIG. 15 can beperformed periodically or continuously. In step 750, the state machine(or controller, or other device) will determine whether the memorysystem is idle. If not, the method of FIG. 15 is completed. If thememory system is idle, then a time stamp for the next set of readcompare points is accessed. In one embodiment, there is one set of readcompare points for the entire system. In another embodiment, each block,word line or other unit of data will have its own set of read comparepoints and each set will have its own time stamp. The first time thatstep 752 is performed, a time stamp for any of the various sets of readcompare points is accessed. Each subsequent iteration of step 752 duringa performance of the process of FIG. 15 will access another set of timestamps for another word line, block, etc. In one embodiment, multiplesets of read compare points can share a common time stamp.

In step 754 of FIG. 15, the system will determine if the accessed timestamp indicates that the associated read compare points are older than apredetermined threshold (e.g., two weeks, two months, etc.). If so, thenthe set of read compare points associated with the currently chosen timestamp are updated in step 756. If the accessed read compare points arenot older than the predetermined threshold, then step 756 is skipped. Instep 758, it is determined whether there are more sets of read comparelevels. If there are more sets of read compare levels that need to beconsidered, then the process loops back to step 752 and the next timestamp for the next set of read compare levels is processed. If there areno more sets of read compare levels that need to be considered in thisperformance of the method of FIG. 15, then the method of FIG. 15 iscompleted.

One set of read compare points can be obtained per word line. The memorycells (or a subset of the memory cells) that reside on one word line canform one or more ECC pages. A portion (e.g. one quarter) of the cellsthat reside on the same word line may constitute an ECC page. In oneembodiment, one set of read compare points per word line will beappropriate for all the ECC pages on that word line. To save time, thesame set of read compare points obtained on one word line may be used onall other word lines in the same block. If information about the time ofthe last update of the read compare points for a given ECC page is notavailable, then the rate at which the read compare points are updated inthe background can be adjusted such that no word line's read comparepoints are updated more often than a predetermined amount of time evenif the memory system is continuously powered up and idle.

FIG. 16 is a flow chart that describes a set of embodiments for updatingread compare levels (step 714 of FIG. 14 or step 756 of FIG. 15). Instep 800, threshold voltage distribution data is determined for apopulation of memory cells. In one embodiment, the threshold voltagedistribution data is determined for all memory cells connected to asingle word line, all memory cells in a block, all memory cells in anarray of memory cells, or another unit of memory cells. In one example,the threshold voltage distribution data provides information about thenumber of memory cells at each measured threshold voltage value. Othertypes and forms of threshold voltage distribution data can also be used.In step 802, the threshold voltage distribution data is smoothed. Anyone of many suitable known functions can be uses to smooth the thresholdvoltage distribution data. For example, a low pass filter can be used tosmooth the data. Other examples of suitable functions are providedbelow. In step 804 of FIG. 16, the derivative of the smoothed data isdetermined. There are many ways and forms to create and storeinformation about the derivative, with no one particular way or formrequired. In step 806, the output of derivative calculation isinvestigated to look for zero crossings. In one embodiment, zerocrossings of the derivative data from negative derivative data valuestransitioning to positive derivative data values, as word line voltageis increased, represent read compare points. In other embodiments, thescale, form or range of the data could be different and the processwould look for other data landmarks (including crossing otherthresholds) as an indication of the read compare points. In step 808,the new read compare points found in step 806 are used to replace theold read compare points. In one embodiment, the new read compare pointsare stored as parameters in registers/latches in the controller 244 orcontrol circuitry 220 to be used immediately. In another embodiment, thenew read compare points are stored as parameters in non-volatile memoryfor future use. The preferred type of non-volatile memory for suchparameters storage is the binary type which would allow more updates asit is more immune to degradation due to program/erase cycles.

The process of FIG. 16 can be completely performed on memory chip 212(e.g., at the direction of state machine 222) or it can be performed bya combination of memory chip 212 and controller 244. In oneimplementation, the controller issues a command to the state machine toupdate the read compare points. In another implementation, the statemachine determines when to update the read compare points. In oneexample, the controller requests the threshold voltage distribution datafrom the memory chip 212 and then the controller issues commands to thememory, receives data from memory that allows it to perform steps802-806. Other divisions of labor can also be used.

FIG. 17 is a flow chart describing one embodiment of determiningthreshold voltage distribution data for a population of memory cells(step 800 of FIG. 16). In one embodiment, the read operation isperformed for all of the memory cells connected to a selected word line.In step 830 of FIG. 17, the minimum value for read compare voltage Vcgris set (e.g., −2.4 volts). In step 832 a read operation is performedusing the Vcgr set in step 830. For example, the process of FIG. 12 isperformed with the current value of Vcgr being applied to the selectedword line. The number of memory cells that conducted (turn on) inresponse to Vcgr being applied to their respective control gates (viathe selected word line) is determined and stored (step 834). Thedifference between the number of memory cells that conducted (turned on)in response to the current Vcgr and the number of memory cells thatconducted (turned on) in response to the previous Vcgr is determined.That difference represents the number of memory cells having a thresholdvoltage at the current Vcgr. The first time that steps 832-836 areperformed, the number of memory cells that conducted (turned on) inresponse to the previous Vcgr is zero. If there are more samples toconsider (step 838), then Vcgr is incremented in step 840 and theprocess loops back to step 832. In one embodiment, Vcgr is incrementedby 0.025 volts. However, other increment sizes can also be used. Whenthe process loops back to step 832, another read operation is performedfor the new Vcgr, the number of conducting memory cells is determined(step 834) and the new delta (step 836) is calculated. When there are nomore samples to collect (e.g., Vcgr=5.0 volts or all memory cells havehad there threshold voltage determined), then the process of FIG. 17 iscomplete. In another embodiment, a maximum Vcgr has been previouslyspecified. If after step 840 the maximum Vcgr has been reached, then allremaining memory cells are assigned this maximum Vcgr. At this point,the data collected is an array of tuples, where each tuple includes athreshold voltage and an indication of the number of memory cells thatare at that threshold voltage. In one embodiment, the process of FIG. 17is performed at the direction of state machine 222.

Distribution function (cell count as a function of control gate voltage)860 of FIG. 18 provides one example of threshold voltage distributiondata that is the result of the process of FIG. 17, which is one exampleof implementing step 800 of FIG. 16. Distribution function 862 of FIG.18, which shows a smoothed version of distribution function 860, is oneexample of the result from step 802 of FIG. 16. FIG. 19 depicts thederivative of distribution function 862, which is an example of theresult of step 804 of FIG. 16. Step 806 includes identifying zerocrossings from negative values to positive values along the waveform ofFIG. 19. Points 870 and 872 are two examples of zero crossings fromnegative values to positive values depicted in FIG. 19, and both can beread compare points. In one embodiment, the zero crossings are obtainedby interpolation between pairs of neighbor derivative data.

FIG. 20 20A is a flow chart that describes an alternative embodiment ofthe process of FIG. 16. In step 900, threshold voltage distribution datais determined for a population of memory cells. Step 900 is similar tostep 800. In step 902, the threshold voltage distribution data issmoothed by convolving the threshold voltage distribution data with afunction. In one set of examples, a weighted function is used. In oneembodiment, a Gaussian function is. In another embodiment, the functionis a truncated Gaussian so that the front and back tails of the Gaussianfunction are removed to look like FIG. 20A 20B. In other embodiments,functions (weighted and not weighted) other than a Gaussian can be used.Note that smoothed distribution function 862 of FIG. 18 provides anexample of smoothing the threshold voltage distribution data byconvolving the threshold voltage distribution data with the Gaussianfunction. In step 904, the derivative of the smoothed data isdetermined. Step 904 is similar to step 804. In step 906, the output ofderivative calculation is investigated to look for negative to positivetransitioning zero crossings in order to identify new read comparepoints. Step 906 is similar to step 806. In step 908, the new readcompare points found in step 906 are used to replace the old readcompare points. Step 908 is similar to step 808.

The table below provides an example set of data representing twenty onepoints along a Gaussian curve used for the convolution operation in step902. As can be seen, the Gaussian serves as a weighting function.

2.73E−12 3.15E−10 2.21E−08 9.39E−07 2.42E−05 0.000379 0.003595 0.0206850.072198 0.152842 0.196254 0.152842 0.072198 0.020685 0.003593 0.0003792.42E−05 9.39E−07 2.21E−08 3.15E−10 2.73E−12

FIG. 21 21A is a flow chart that describes an alternative embodiment ofthe process of FIG. 16. In step 920, threshold voltage distribution datais determined for a population of memory cells. Step 920 is similar tostep 800. In step 922, the threshold voltage distribution data issmoothed by convolving the threshold voltage distribution data with askewed function. In one embodiment, the function is a Gaussian functionthat will be skewed as described below; however, other functions canalso be skewed and used in step 922. In step 924, the derivative of thesmoothed data is determined. Step 924 is similar to step 804. In step926, the output of derivative calculation is investigated to look forzero crossings in order to identify new read compare points. Step 926 issimilar to step 806. In step 928, the new read compare points found instep 926 are used to replace the old read compare points. Step 928 issimilar to step 808.

FIG. 7 shows the threshold voltage distributions for each state as beingsymmetrical. However, in many cases, the threshold voltage distributionsare not symmetrical. It has been observed in some cases that one side ofa threshold voltage distribution may have a different slope than theother side of the threshold voltage distribution. For example, thethreshold voltage distribution waveform of FIG. 21A 21B has a moregradual slop on side 930L and a more steep slope on side 930R. Becauseof the difference in slopes of the two sides of the threshold voltagedistribution, some embodiments will skew the Gaussian function in orderto accommodate the skew in distribution data. One example of skewing theGaussian function is to multiply it by a line characterized by theequation Y=m×+b, where m and b could be positive or negative. In oneimplementation, the skewing is constant so that the Gaussian function ismultiplied by the same equation along the entire range of thresholdvoltages. In another embodiment, the equation for the line can changeover the range of threshold voltages. In one option Y=m×+b is used forlower threshold voltages (lower data states) and Y=−m×+b is used forhigher threshold voltages (higher data states). One reason for doingthis is that the steep slope can be at the upper end of a thresholdvoltage distribution for higher states (possibly because of dataretention issues) so the process may want to give more weight to higherthreshold voltages. On the other hand, the steep slope can be at thelower end of a threshold voltage distribution for lower states (possiblybecause of program disturb issues) so the process may want to give moreweight to lower threshold voltages. In another option, the equation forthe line can change for each data state by adjusting m from a highpositive number toward zero and then to a high negative number whengoing from low data states to high data states.

In another embodiment, the width of the Gaussian function can be changedby changing the sigma for the Gaussian function. For example, one sigmacould be used for low data states and a different sigma could be usedfor high data states. Alternatively, the sigma could change for eachdata state.

FIG. 22 is a flow chart that describes an alternative embodiment of theprocess of FIG. 16. In step 950, threshold voltage distribution data isdetermined for a population of memory cells. Step 950 is similar to step800. In step 952, the threshold voltage distribution data is smoothed byusing a weighted moving average. One example is to perform a convolutionof the threshold voltage distribution data with a rectangular function.Other means for calculating a weighted moving average can also be used.In step 954, the derivative of the smoothed data is determined. Step 954is similar to step 804. In step 956, the output of derivativecalculation is investigated to look for zero crossings in order toidentify new read compare points. Step 956 is similar to step 806. Instep 958, the new read compare points found in step 956 are used toreplace the old read compare points. Step 958 is similar to step 808.

FIG. 23 is a flow chart that describes an alternative embodiment of theprocess of FIG. 16. In step 1000, threshold voltage distribution data isdetermined for a population of memory cells. Step 1000 is similar tostep 800. In step 1002, the threshold voltage distribution data issquared. This may serve to provide more contrast for the data. In step1004, the square of threshold voltage distribution data is smoothedusing any of the methods discussed above. In step 1006, the derivativeof the smoothed data is determined. Step 1006 is similar to step 804. Instep 1008, the output of derivative calculation is investigated to lookfor zero crossings in order to identify new read compare points. Step1008 is similar to step 806. In step 1010, the new read compare pointsfound in step 1008 are used to replace the old read compare points. Step1010 is similar to step 808.

FIG. 24 is a flow chart describing another embodiment of determiningread compare points. In step 1040, an initial set of new read comparepoints are determined using the process of FIG. 20 or 21, with a largersigma for the Gaussian function. By using the larger sigma, the processof determining a new set of read compare points will be less precise. Instep 1042, the original data of threshold voltage distribution data (seesteps 900, 920, etc) is accessed. In step 1044, minima are searched forin the original data of threshold voltage distribution data in thevicinity of the initial set of new read compare points from step 1040.For example, the wave form 860 of FIG. 18 could be searched for minimawithin the vicinity of the initial set of new read compare points. Inthis manner, the initial set of new read compare points serves as a seedfor a search algorithm.

FIG. 25 is a flow chart describing another embodiment of determiningread compare points. In this embodiment, the new read compare points areadjusted by one or more offsets. In step 1100, the one or more offsetsare determined. In step 1102, an initial set of new read compare pointsare determined using the process of FIGS. 16, 20, 21, 22, 23 or anotherprocess. In step 1104, the initial set of new read compare points areadjusted by the one or more offsets. In one example, one offset is usedto adjust all of the new read compare points. In another embodiment,each new read compare point is adjusted by a different offset. In yetanother embodiment, groups of new read compare points are adjusted by adifferent offset for each group.

Steps 1120-1134 provide one example of a process for determining one ormore offsets (step 1100) using device characterization. In step 1120,one or more memory chips 212 are cycled many times (e.g., thousand ortens of thousands of times). For example, the memory is programmed anderased as many times as the maximum number of cycles allowed byspecifications of the product (e.g., four thousand or other number). Instep 1122, a data pattern is written to the memory cells. In step 1124,the one or more memory chips 212 are baked in an oven accelerate chargeloss/gain. In step 1126, new read compare points are determined usingany of the methods described above. In step 1128, a read process isperformed using the new read compare points. In step 1130, the datameasured in step 1128 is compared to the actual data. In step 1132, anerror is calculated. In step 1134 adjustments are made to the readcompare points and the error is recalculated. Trial and error can beused to make a large amount of guesses at the adjustments in order tominimize the error. A computer can be used to guess at the adjustmentsand calculate the new error in the attempt to minimize the error. Theadjustments made to minimize the error are the offset to be used in step1104. In one embodiment, each read compare points has a separate offset.In another embodiment, all of the calculated offsets are averaged tocalculate a single offset foe all read compare points.

Another method that can be employed to determine each read point'soffset value individually does not require any pre-characterization ofthe memory. This method can use any of the procedures discussed above tofind the zero crossing of the derivative of the smoothed distributionfunction. It may be preferable to use a non-skewed function (e.g. aregular Gaussian) for the smoothing operation in order not to end upover-skewing the read levels. In this method, once the minima of thesmoothed distribution function are determined, the values at X volts tothe right and to the left of each minimum are observed and compared toeach other. The difference in the two values or the ratio of the valuescan be used to obtain the sign and the magnitude of the offset for eachand every read level. The tails of each distribution can often bemodeled by an exponential function. A simple mathematical study can showthat when two neighbor distributions merge into one another with one'supper tail overlapping the other's lower tail what happens to theposition of the minimum of the sum of the two distributions (which isthe only distribution function that can be measured if one does not haveprior knowledge of the data was written to the page). Typically, theideal read level that minimizes the error is where the two distributionscross each other. However, we do not have information about the twoindividual distributions, as we do not know the data that was written tothe page. As a result we have to rely on the only information that isavailable which is the sum or superposition of all the states'distributions. The superposition distribution (e.g. plot 860 of FIG. 18)is the only available information. Once the local minima of thedistribution function or of the smoothed function are obtained, one canlook up values of the distribution function or the smoothed distributionfunction at, for example, 75 mV to the right and to the left of eachlocal minimum. The sizes of these surrounding values can be comparedwith one another (by dividing one by the other and obtaining a ratio R)to gauge the asymmetry in the tails of the two neighbor distributions.With this asymmetry gauged, and a prior mathematical analysis that hasalready shown how much offset is required for various degrees ofasymmetry in shape of the upper tail of State N as compared to the shapeof the lower tail of State N+1 distributions. The required offset valuescan be looked up in a table whose input is the value of the ratio R. Inanother embodiment, the table's input will be the value of the ratio R1,in addition to information such as the maxima of the two neighbor peaksof the smoothed function, or the ratio of each one of these maxima tothe smoothed minimum. This maximum to minimum ratio, and there are twoof them per read level, are a good gauge of how wide each state'sdistribution is. The width of each of the two neighbor states may have abearing on the offset value for the read level residing between the twostates.

The processes discussed above for reading data, including determiningnew read compare points, can be used to read data after the data isprogrammed or can be used as part of a verify process duringprogramming.

The foregoing detailed description of the invention has been presentedfor purposes of illustration and description. It is not intended to beexhaustive or to limit the invention to the precise form disclosed. Manymodifications and variations are possible in light of the aboveteaching. The described embodiments were chosen in order to best explainthe principles of the invention and its practical application, tothereby enable others skilled in the art to best utilize the inventionin various embodiments and with various modifications as are suited tothe particular use contemplated. It is intended that the scope of theinvention be defined by the claims appended hereto.

What is claimed is:
 1. A memory system, comprising: a plurality ofnon-volatile storage elements; and one or more managing circuits incommunication with said plurality of non-volatile storage elements, saidmanaging circuits operate said plurality of non-volatile storageelements including: accessing threshold voltage distribution data for apopulation of non-volatile storage elements; operating on the thresholdvoltage distribution data to create transformed threshold voltagedistribution data; identifying read compare points based on thetransformed threshold voltage distribution data; replacing old readcompare points with the identified read compare points; and performingone or more read operations using the identified read compare points. 2.A memory system according to claim 1, wherein said plurality ofnon-volatile storage elements are arranged in NAND strings.
 3. A memorysystem according to claim 1, wherein said operating on the thresholdvoltage distribution data comprises: calculating derivative informationfor the threshold voltage distribution data, the read compare points areidentified from the derivative information.
 4. A memory system accordingto claim 3, wherein said operating on the threshold voltage distributiondata comprises: smoothing the threshold voltage distribution data priorto calculating the derivative information.
 5. A memory system accordingto claim 4, wherein said smoothing the threshold voltage distributiondata comprises: convolving the threshold voltage distribution data witha truncated Gaussian function to create an interim set of data, thederivative information is calculated from the interim set of data.
 6. Amemory system according to claim 4, wherein said smoothing the thresholdvoltage distribution data comprises: smoothing the threshold voltagedistribution data using a weighted function to create an interim set ofdata, the derivative information is calculated from the interim set ofdata.
 7. A memory system according to claim 6, wherein: the weightedfunction is a truncated Gaussian function multiplied by a sloped line.8. A memory system according to claim 4, wherein said one or moremanaging circuits square the threshold voltage distribution data priorto said smoothing.
 9. A memory system according to claim 4, wherein saididentifying read compare points includes: identifying and storingnegative to positive zero crossings in the derivative information.
 10. Amemory system according to claim 1, wherein said operating on thethreshold voltage distribution data to create transformed thresholdvoltage distribution data comprises: convolving the threshold voltagedistribution data with a Gaussian function.
 11. A memory systemaccording to claim 10, wherein said Gaussian function is a skewed andtruncated Gaussian function.
 12. A memory system according to claim 1,wherein said operating on the threshold voltage distribution data tocreate transformed threshold voltage distribution data comprises:convolving the threshold voltage distribution data with a function. 13.A memory system according to claim 1, said operating on the thresholdvoltage distribution data to create transformed threshold voltagedistribution data comprises: squaring the threshold voltage distributiondata.
 14. A memory system according to claim 1, wherein said one or moremanaging circuits apply one or more offsets to the read compare points.15. A memory system according to claim 1, wherein said one or moremanaging circuits apply a changing offset to the read compare points.16. A memory system according to claim 1, wherein said one or moremanaging circuits operate said plurality of non-volatile storageelements further comprising: searching for minima in the thresholdvoltage distribution data near the read compare points; replacing oldread compare points with the minima; and performing one or more readoperations using the minima.
 17. A non-volatile storage apparatus,comprising: an array of non-volatile storage elements; and a managingcircuit in communication with said array of non-volatile storageelements, said managing circuit operates said array of non-volatilestorage elements including: determining threshold voltage distributiondata for a population of non-volatile storage elements; smoothing saidthreshold voltage distribution data using a weighted function to createan interim set of data; determining a derivative of the interim set ofdata; identifying new read compare values based on negative to positivezero crossings of the derivative; and performing one or more readoperations using the new read compare values.
 18. A non-volatile storageapparatus according to 17, wherein: said identifying new read comparevalues based on negative to positive zero crossings of the derivativeincludes applying one or more offsets to the negative to positive zerocrossings and storing the offset negative to positive zero crossings asthe new read compare values, said new read compare values areindications of voltage levels for differentiating between multiple datastates for multi-state flash memory.
 19. A non-volatile storageapparatus, comprising: an array of non-volatile storage elements; and amanaging circuit in communication with said array of non-volatilestorage elements, said managing circuit operates said array ofnon-volatile storage elements including: determining threshold voltagedistribution data for a population of flash memory devices; convolvingsaid threshold voltage distribution data with a Gaussian function tocreate an interim set of data; determining a derivative of the interimset of data; identifying negative to positive zero crossings of thederivative; storing new read compare values based on the identifiednegative to positive zero crossings of the derivative; and performingone or more read operations using the new read compare values.
 20. Anon-volatile storage apparatus according to 19, wherein: said storingnew read compare values based on the identified negative to positivezero crossings of the derivative includes applying one or more offsetsto the negative to positive zero crossings and storing the offsetnegative to positive zero crossings as the new read compare values. 21.The memory system of claim 1, wherein: the plurality of non-volatilestorage elements comprises a three-dimensional array of storageelements.
 22. The memory system of claim 1, wherein: the plurality ofnon-volatile storage elements comprises a three-dimensional array ofmemory cells.
 23. The memory system of claim 1, wherein: the pluralityof non-volatile storage elements are arranged in a three-dimensionalmemory structure.
 24. The non-volatile storage apparatus of claim 17,wherein: said array of non-volatile storage elements comprises athree-dimensional array of storage elements.
 25. The non-volatilestorage apparatus of claim 17, wherein: said array of non-volatilestorage elements comprises a three-dimensional array of memory cells.26. The non-volatile storage apparatus of claim 19, wherein: said arrayof non-volatile storage elements comprises a three-dimensional array ofstorage elements.
 27. The non-volatile storage apparatus of claim 19,wherein: said array of non-volatile storage elements comprises athree-dimensional array of memory cells.